In a typical data communications system, data must be sent from some driving latch and captured at a receiving latch. FIG. 1 shows basic block diagrams of such a data communications system implemented as either a chip-to-chip interface 100 or an on-chip interface 120. In a chip-to-chip interface 100, various components such as off-chip drivers (e.g., 103) and receivers (e.g., 105), transmission lines (e.g., 104) (printed wiring boards and/or cables), and some amount of logic circuitry (e.g., 106) will exist in the communications path. In contrast, an on-chip interface will typically comprise only internal logic gates (e.g., 109, 110, and 111) in the communications path.
Either of these communications systems may be implemented using SOI technology which give rise to the “history effect” which cause pulse width distortions. The history effect occurs when an SOI gate sustains a steady logic state (logic one or logic zero). The steady logic state tends to modify the body charge on SOI devices which in turn changes the gate threshold voltage which determines voltage levels at which logic state switching occurs. If one logic transition to a logic state occurs with one body charge condition and the next transition occurs with another different body charge condition, then the resulting pulse width will be modified (history effect) which may lead to timing errors. This history effect is typically fixed by using body-contacted devices; however, at high enough frequencies the body (dis)charge time constant is larger than the pulse width so the history effect may remain even with body-contacted devices. If the SOI devices are not body-contacted, then they are floating-body devices and as such have a much longer body charge/discharge time constant which may be exploited.
FIG. 2 is a timing diagram that illustrates the pulse modification in a SOI device due to the history effect discussed above. Of particular interest is what happens to the data as it passes through the blocks labeled “logic gates” in FIG. 1 since these blocks have the greatest impact on the SOI history effect depending on the total delay through these sections. To explain the pulse modification on an input (trace 201) due to the history effect, some basic time delays through the logic gates are defined. Propagation delay T prop is the amount of time that it takes for a signal to travel through the logic gates. The amount of delay due to the history effect is defined as T hist. Ideally, (trace 202) the first and second consecutive logic state transitions at a given frequency will propagate through the logic gates with a delay of T prop as shown in FIG. 2. However, in SOI technology, the first logic transition is delayed (T prop+T hist) whereas the second consecutive logic transition is delayed by only T prop resulting in the pulse distortion shown in trace 203 FIG. 2.
In an exemplary chip-to-chip interface 100, the logic gates 106 after the transmission line receiver 105 of FIG. 1 is replaced by a programmable delay circuitry which may selectable delay from zero picoseconds (0 psec)–500 psec for correcting the delay differences between parallel data channels. If the history effect caused a 10% history effect, then the delay circuitry would have a worst case 50psec pulse distortion. These channels may be clocked from 2 Gigabits per second (Gbps) to 5Gbps. At 5 Gbps, a 200 psec pulse would compress to 150 psec. This amount of pulse distortion along with the uncertainties of jitter and latch setup/hold times will result in high bit-error rates if un-compensated. One method of reducing the pulse distortion produced in such delay circuitry is to replace the delay circuitry with logic (not shown) that is clocked with multiple phases of a phase shifted clock configured to emulate the function of the delay circuitry. This resolves the problem because now a continuous pattern is being driven through the logic and the body voltage of the field effect transistor (FET) devices in the clocked logic maintains a constant charge and thus a fixed threshold voltage. However, this solution requires far more power and is thus less efficient requiring more power which is exacerbated by high frequency.
There is, therefore, a need for a method and circuitry to minimize the shift in gate threshold in SOI CMOS devices while maintaining the power efficiency of the delay circuitry for de-skewing parallel data channels.